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8-bit MCUs Hone Competitive Edge with Evolving Architectures
Data:2014-12-10 , 
Evolutionary changes in 8-bit MCU architectures are helping them stay at the head of the pack in terms of unit sales in the overall MCU market. In many applications, 8-bit MCUs are successfully fending off competition from 32-bit MCUs — and not just in instances where designs require very small form-factors, ultra-low energy consumption, low pin-out and very low prices. In some instances, 8-bit MCUs actually outperform their 32-bit competitors. 

Market analyst firm IC Insights, Phoenix, Arizona, forecasts that 8-bit MCUs will continue to have the largest unit shipment volume in the microcontroller business until at least 2018. On the other hand, shipments of 32-bit MCUs are growing at 9.5 percent — a much higher annual percentage rate than 8-bit devices. 

Some of the architectural changes — such as making 8-bit MCUs easier to program in C code — fall into the category of keeping up with a changing world. Other changes have a “back to the future” feel about them, such as returning to the concept of closed-loop feedback control with the MCU’s peripherals executing tasks without CPU intervention. 

Autonomous MCU peripherals have been around for quite some time, but MCU vendors dedicated to fully supporting their 8-bit product lines keep adding sophisticated techniques that move the meaning of the term “autonomous peripheral” into a new realm. 

Configurable logic cells 

The most recent set of innovations comes from Microchip Technology in what the company calls “functional enablement.” It starts with the concept of “core-independent peripherals” — peripherals specifically designed to work as much as possible without CPU intervention — and to efficiently communicate with each other whenever necessary. 

Enhanced peripheral-to-peripheral communication is implemented using configurable logic cells (CLCs). Microchip’s chip architects created this communication flexibility so that embedded systems designers can use the core-independent peripherals to implement closed-loop feedback control systems in hardware. In addition to lightening the processing load for the CPU, this has other benefits including: faster response time, fewer lines of application code, lower energy consumption, and reduced memory requirements for the MCU. 

CLC modules have eight signals available as inputs to the configurable logic cell and each input signal can vary from device to device. Up to four inputs can be selected at a time and this is done using four 8-input multiplexers to pass the input signals on to the data gating stage of the CLC. Figure 1 shows the initial configuration step of a CLC with input signals selected with the CLCxSEL0 and CLCxSEL1 registers. 

Subsequent steps with a configuration tool create the CLC’s complete functionality. 

Image of Configurable Logic Cell

Figure 1: Configurable Logic Cell at the first stage of configuration. 

Closed-loop control 

The functional enablement concept starts with identifying the common functional components that could exist in any embedded application. These include: Power conversion, timing, sensor interface, motor control, output and signal generation, communications, human interface, and safety (to comply with regulations involving software interrupts, for example). 

It is important to note that Microchip’s functional enablement moves the meaning of the term “autonomous peripheral” into a new realm. As a result of the CLC and the manner in which core-independent peripherals are implemented on chip, the result is not simply a peripheral that acts more or less independently from time to time to execute a single function. Instead, the peripheral — or combinations of peripherals — can be combined dynamically as needed by the designer. 

Applications 

An example of core-independent peripherals being employed for differing purposes is Microchip’s numerically-controlled oscillator (NCO). Although typically used in lighting-control applications, it can also be used in conjunction with other existing peripherals on the device to implement certain types of data transmission/reception applications or even facilitate higher resolution PWMs. 

Conventional PWMs start losing effective resolution at relatively low-switching frequencies. The smallest incremental change in pulse width achievable by a conventional PWM with a 16 MHz system clock speed, for example, is 62.5 ns. If the fastest available PWM clock is one-fourth the oscillator frequency (FOSC/4), then this increases to 250 ns. A PWM with an incremental pulse width change of as little as 15 ps can be constructed on an MCU with core-independent peripherals, however, by using a numerically-controlled oscillator (NCO) in conjunction with the CLC. 

A simplified block diagram illustrating this technique is shown in Figure 2. The output controller block is based on a CLC. 

Although the NCO cannot produce a PWM signal by itself, its behavior can be changed by adding a CLC-based output controller to produce the desired PWM output. The NCO determines the pulse width. A conventional on-chip PWM can be used as a clock source to trigger the PWM period. 

The control logic in the CLC is used to set an output when the switching clock indicates that it is time for the next pulse. The CLC clears the output to complete the pulse once the NCO overflows. 

Image of high-resolution PWM

Figure 2: High-resolution PWM implemented with an NCO and CLC-based output controller. 

Any number of clock sources could be used (e.g., timers or even external signals), and in some applications an external trigger may be the best choice to start the pulses. A zero-current detection circuit, for example, would be appropriate when building a power supply. An example of a core-independent-peripheral MCU that works in this type of application because it integrates CLC, PWM, and NCO blocks is the PIC16F1509-I/SS

To get started with this type of design approach, the PIC10F32X development board is a useful tool. It is factory programmed with NCO and CLC demonstration software and includes a prototype area for application development. 

While the strategy of creating closed-loop feedback control systems with peripherals has many advantages, sometimes CPU intervention really is required — when the system is experiencing uncharacteristic behavior, for example. Hardware limit timers address this possibility. 

Most peripherals initiate an activity of some sort, but hardware limit timers are typically used to wait for an event to occur — and do something in response to an event that does not happen. Protecting a MOSFET from damage in a power supply application is a good example. LED lighting applications require fairly high-resolution power supplies. Using Microchip’s core-independent peripherals, a PWM can be configured to drive a FET pair without CPU intervention under normal circumstances. In the case of a PWM failing to turn off when it should, hardware limit timers, op amps, and comparators can be employed to ensure that the MOSFET is not damaged. 

The timer’s basic job is to monitor whether the PWM turns off after a certain interval as it would in normal operation. If it does not, the hardware limit timer triggers an interrupt asking the CPU to check out the cause of the abnormality, which could be a glitch or something more serious. 

If the CPU determines that the condition is one in which the PWM should be shutdown, the entire shut-down operation takes about 80 ns because it is being executed in hardware: The comparator can flip in 50 ns; accounting for the slew rate of the integrated op amp adds another 30 ns. 

A software implementation would not be nearly as fast because there would be two- or three-clock cycles of latency involved in issuing an interrupt plus the time required to issue an instruction. In some instances, there also might be a delay caused by a higher priority interrupt. 

Microchip’s 8-bit PIC16F170X/171X family was among the first to feature core-independent peripherals. Members of this family can be used for many applications, including intelligent lighting control. A typical choice might be the PIC16F1703-I/SL

A companion product is the DM330014 LED Lighting Development Kit. 

The 32-bit challenge 

In applications where 8-bit and 32-bit MCUs compete, the argument of 32-bit advocates has been that their low-end devices are price-competitive with 8-bit MCUs (and that in high-volume purchases they may even be priced lower). A careful examination of 32-bit MCUs that are cost competitive with 8-bit MCUs, however, shows that they are low-end devices that integrate only basic peripherals. Adding more peripherals adds to the cost, however, so matching low-end 32-bit devices to peripheral-rich 8-bit devices may not always yield an apples-to-apples comparison. 

Low-end 32-bit MCUs are left with one alternative: Executing in software what 8-bit devices with a cohort of peripherals do more efficiently in hardware. That is, fewer lines of code, faster response time, faster time-to-market with the application, and lower energy consumption because more executing instructions requires more clock cycles. Executing a function faster in hardware also allows the MCU to go into sleep mode sooner — and stay there longer. 

Instruction sets and pipelining 

Although Microchip can take credit for the latest innovations in 8-bit architectures, it is by no means the only company with a strong commitment to making 8-bit MCUs capable of delivering superior performance. 

Silicon Labs has re-architected the basic 8051 MCU architecture into a pipelined complex instruction set computing (CISC) device with Fetch/Decode/Execute pipe stages. 

The instruction set architecture has been modified to maximize instruction throughput while retaining 100% object code compatibility. This “hard wired” implementation provides numerous benefits over the original micro-coded version. 

Silicon Labs’ instruction set itself has also evolved. It is now mapped to two-stage pipeline increased throughput and maintains an 8-bit program memory width. The result is an MCU that executes most instructions within 1 or 2 clock cycles and delivers 20 to 25 times the performance of the original 8051 core. 

The pipelined architecture provides computational performance that can be favorably compared with more advanced CPU architectures. Most RISC-based MCUs, for example, are register-based and allow only arithmetic logic unit (ALU) operations on values stored in the register file. This means that in order to “AND” two values together, the values must be moved to the register file before they can be operated on. Silicon Labs’ 8051 architecture, on the other hand, performs this operation directly on values stored in peripheral registers. This enables the MCU to perform fast control functions. 

In addition to proactively supporting its 8-bit product line, Silicon Labs has also carved out a market niche in low-power operation. Members of its C8051F96x family such as theC8501F969-A-GM integrate an on-chip DC-DC converter that reduces active mode power by 40 percent and offers much higher efficiency voltage conversion than a linear regulator for increased battery life in mobile applications and applications where mains power is not available. 

Conclusion 

Although 8-bit MCUs are being replaced in large numbers by 32-bit MCUs for compute-intensive applications, they still offer many attractive features to system designers. IC companies with robust 8-bit product lines have successfully evolved architectures and instruction sets to keep 8-bit MCUs competitive. Perhaps the most important innovations are in the area of on-chip peripherals that provide hardware execution when 32-bit MCUs that are price-competitive must execute in software. Enhanced techniques for communication between peripherals and new kinds of peripherals are giving the 8-bit devices an even greater advantage in cost-sensitive applications that require low-energy consumption. 
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